1. Technical Field
The disclosure relates generally to semiconductor device fabrication, and more particularly, to methods of electrolytic plating used in semiconductor device fabrication.
2. Background Art
Typical semiconductor integrated circuit (IC) devices, and particularly, ultrafine semiconductor IC devices, include a multilayer wiring structure having patterns comprising a low resistance material employed to interconnect numerous discrete semiconductor devices formed on a substrate. Often, for multilayer wiring structures having copper wiring patterns, fabrication involves wiring trenches or vias formed in advance within a silicon oxide film or within an interlayer dielectric film made of a low-permittivity (low-k) material. The wiring trenches or vias are then filled with a metal layer such as copper and any excess metal is removed by chemical-mechanical polishing.